Traditionally, data access related to a memory device (e.g., a flash memory device, among others) can be implemented by employing a Logical Block Addressing System (LBASYS) to facilitate access to data. In a LBASYS enabled memory device, a logical block address (LBA) typically can be logically related to a physical block address (PBA). The use of a LBA enables access to a PBA through translation of the “physical” storage location address to, or from, a “logical” storage location address as is well known in the art. Thus, an address translation component (e.g., an address translation process, controller, . . . ) can associate dynamically changing PBAs with a more static LBA. This enables hiding some of the complexities of wear leveling, bad erase block management (BBM), or memory data access (e.g., read, write, erase, . . . ) at the user side of a LBASYS interface by obfuscating a changing PBA behind a more static LBA.
Historically, the LBASYS developed in response to traditional electromechanical memory systems (e.g., the increasing capacity of physical disk drive systems in computer systems) becoming very large. In order to address these large drives within the existing operating system memory addressing limitations, multiple logical drives were implemented on single physical drives. Thus, the LBASYS became an ad hoc industry standard and after arriving technologies implemented the LBASYS even where newer operating systems could operate without them. This legacy LBASYS also was applied to later arriving non-electromechanical memory systems. For example, it has been common practice to employ LBASYS in NOR and NAND flash memories, among others. Employing a legacy LBASYS however has conventionally increased the time to access data on a memory device because of the need to translate between a LBA and a PBA when accessing memory.
Generally, information can be stored and maintained in one or more of a number of types of storage devices, such as memory devices. Memory devices can be subdivided into volatile and non-volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), and the like. Non-volatile memory devices can maintain their information whether or not power is maintained to the memory devices. Non-volatile memory devices include, but are not limited to, flash memory, read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), non-volatile RAM, and the like.
The memory cells of a memory device can typically be arranged in an array. A memory cell can be placed at each intersecting row and column in the array. Typically, a particular memory cell can be accessed by activating its row and then writing the state of its column or reading the state of the memory cell. Memory sizes can be defined by the row and column architecture. For example, a 1024 row by 1024 column memory array can define a memory device having one megabit of memory cells. The array rows can be referred to as wordlines and the array columns can be referred to as bitlines.
In memory cells, one or more bits of data can be stored in (e.g., a write) and read (e.g., a read) from respective memory cells. Additionally, one or more bits of data can be erased from (e.g., erase) respective memory cells or blocks of cells (e.g., erase block). The basic memory operations (e.g., read, write, erase, . . . ) to access memory cells and data associated therewith can be commonly performed by application of appropriate voltages to certain terminals of the memory cells. In a read or write operation the voltages can be applied so as to cause a charge to be removed, stored, or sensed in/from a charge storage layer of the memory cell. Further, higher level memory operations can comprise a plurality of basic memory operations to facilitate more complex data access (e.g., a data compaction operation can comprise reading the data from a series of data locations (e.g., reading a plurality of data locations in a data page or erase block) and writing select portions of the read data to a new data location (e.g., writing a plurality of data locations in a new page or new erase block) to store only still relevant data; a garbage collection operation can comprise a data compaction operation followed by erasing data from the old collection of data locations (e.g., erasing a plurality of data locations in the old page or old erase block) to free that space for other data access operations, among others).
The use of portable computer and electronic devices has greatly increased demand for high memory capacity, efficient and reliable memory devices. Digital cameras, digital audio players, personal digital assistants, and the like, generally seek to employ large capacity memory devices (e.g., flash memory, smart media, or compact flash, among others). Many modern computer based devices employ electronic memory devices in which asymmetric data access is typical, for example, in some computing environments read operations occur more frequently than write operations. Where memory operations are asymmetric, direct access to a PBA can decrease data access times in comparison to a LBASYS because time (e.g., computing cycles) to translate between a LBA and a PBA can be eliminated in the data access operation (e.g., read, write, . . . ). Faster access times can translate into higher data throughput in memory devices and improved performance for an end user device.
It is desirable to improve data access performance associated with memory devices. It is also desirable to reduce the amount of time associated with locating a physical memory location to facilitate improved data access performance, while achieving a user-friendly interface.